1. Field of the Invention
The present invention relates in general to a flat panel display, and more particularly, to a flat panel display with a structure preventing electrode line openings.
2. Description of the Related Art
Liquid crystal displays (LCDs) have the advantages of low power consumption, thin profile, light weight and low driving voltage and have been put to practical use with personal computers, navigation systems, and projectors. Owing to dielectric anisotropy and conductive anisotropy of liquid crystal molecules, molecular orientation of liquid crystals can be shifted under an external electronic field, such that various optical effects are produced. Generally, in an LCD panel, a liquid crystal layer is disposed between two transparent substrates, such as glass substrates. One of the transparent substrates has driving devices, such as thin film transistors (TFTs) disposed thereon. In the LCD panel, the array composed of pixel areas is defined by interlaced gate lines and date lines, and each pixel area has one TFT and one pixel electrode.
Generally, TFTs are usually classified into top gate and bottom gate types according to the TFT structure, and the bottom gate type TFT may further be classified into etch-back type and etch-stopper type, wherein the etch-stopper type TFT structure has a protective film disposed on the semiconductor layer to protective the channel layer.
Referring to FIGS. 1-3, in which FIG. 1 is a plane view of a conventional etch-stopper type TFT structure in a flat panel display, FIG. 2 is a cross-section along the 1-1′ line in FIG. 1, and FIG. 3 is a cross-section along the 2-2′ line in FIG. 1. The TFT structure includes a gate electrode 102a and a gate line 102b. Moreover, a source electrode 110a and a drain electrode 110b are respectively disposed on both sides of the gate electrode 102a. The source electrode 110a extends outwardly to form a data line 110c perpendicular to the gate line 110b. A passivation layer may be formed in two areas. One area is over the TFT, as the area T shown in FIG. 1. Another one is the overlapping area between the gate line 102b and the data line 110c, as the area P shown in FIG. 1. Here, in order to clearly differentiate the passivation layer formed in area T from the area P, the passivation layer formed in area T is referred to as channel protective layer (stopper-insulator, I-stop) and that formed in area P is referred to as etching buffer layer. A cross-section of area T is shown in FIG. 2. The channel protective layer 112a is disposed on the semiconductor layer 106 overlying the gate electrode 102a. Doped semiconductor layers 108a, 108b are respectively disposed on both sides of the channel protective layer 112a to serve as ohmic contacting layers for the source electrode 110a and the drain electrode 110b. Additionally, the etching buffer layer 112b formed in area P is disposed between the semiconductor layer 106 overlying the gate line 102b and the data line 110c. 
However, the etching buffer layer 112b formed in area P is defined by rear exposure process using the underlying gate line 102b as a photomask, thus inducing lateral etching when the data line 110c overlying the buffer layer 112b is etched, resulting the data line 110c opening. FIG. 4 is an enlarged diagram of area P shown in FIG. 1. The etching buffer layer 112b with linear edges 112′ may induce lateral etching. That is, etching is induced along a direction perpendicular to the direction of the data line 110c (as arrows depict in FIG. 4), resulting in data line 110c opening.